1. Field of the Invention
The present invention relates to a semiconductor device for driving an inductive load, such as a motor.
2. Description of Related Art
FIG. 13 is a diagram showing an example of a motor drive circuit 100. Referring to FIG. 13, Q1, Q2, and Q3 are power transistors connected to a power supply node VM. Q4, Q5, and Q6 are power transistors connected to the ground potential node. A motor 200 is a load. MU, MV, and MW are input terminals of the motor 200. LU, LV, and LW are coils of the respective phases of the motor 200. VM is a power supply node supplied a voltage of the power source for driving the motor 200.
The motor drive circuit 100 shown in FIG. 13 has the power transistors three-phase-connected. The transistors Q1 and Q4 are connected to each other in series, the collector of the transistor Q1 is connected to the power supply node VM, a connection point W between the transistors Q1 and Q4 is, through a terminal 23, connected to the terminal MW of W-phase coil LW of the motor 200 through a terminal 23, and the emitter of the transistor Q4 is connected to the ground potential node through a resistor 17.
The transistors Q2 and Q5 are connected to each other in series. The collector of the transistor Q2 is connected to the power supply node VM. A connection point V between the transistor Q2 and the transistor Q5 is, through a terminal 22, connected to the terminal MV of the V-phase coil LV of the motor 200. The emitter of the transistor Q5 is connected to the ground potential node through the resistor 17.
The transistors Q3 and Q6 are connected to each other in series. The collector of the transistor Q3 is connected to the power supply node VM. A connection point U between the transistors Q3 and Q6 is, through a terminal 21, connected to the terminal MU of the U-phase coil LU of the motor 200. The emitter of the transistor Q6 is connected to the ground potential node through the resistor 17.
In the described structure, a small-signal circuit 40, to be described later, turns the transistors Q3 and Q5 on and the transistors Q1, Q2, Q4, and Q6 off. Thus, a current flows from the coil LU to the coil LV. As a result, a magnetic field is generated by the coils LU and LV in a predetermined direction. A rotor comprising a permanent magnet is rotated in the direction of the generated magnetic field.
FIG. 14 shows a state shifted from the state shown in FIG. 13 with the transistor Q3 turned off and the transistor Q1 turned on. At this time, the current is switched to flow from the coil LW to the coil LV. The current that flows into the coil LU is interrupted. Inductive energy stored in the coil LU makes the voltage at the terminal 21, that is the collector (the connection point U) of the transistor Q6, negative, as shown FIG. 15. FIG. 15 is a graph showing the waveform of the output voltage from the phase U (the terminal 21) of the motor drive circuit.
FIG. 16 is a plan view showing an example of a semiconductor device for driving a motor. Referring to FIG. 16, a chip 100 of the semiconductor device includes a motor drive circuit. Q1 to Q3 are power transistors connected to the power supply node VM. Q4 to Q6 are power transistors connected to the ground potential node. The chip, i.e., semiconductor body, has an end, i.e., side surface, 3 and aluminum wiring layers 5, 6, 8, 9, and 14. Each of the power transistors Q4 to Q6 has a respective area 10 on the semiconductor body. Each of the power transistors Q1 to Q3 has a respective area 11 on the semiconductor body. The epitaxial layer includes an N-type region 12, a resistor 17, and a small-signal circuit 40. A resistor region 30 is located in the small-signal circuit 40. A transistor region 31 is located in the small-signal circuit 40. Although the small-signal circuit 40 includes various circuits, the resistor region 30 and the transistor region 31 are illustrated as examples.
FIG. 17 is a cross-sectional view of the semiconductor device taken along line XVII--XVII of FIG. 16. A P-type semiconductor substrate 1 has on its surface an N-type epitaxial layer. A semiconductor body comprises the semiconductor substrate 1 and the epitaxial layer. An embedded region 2 is located between the semiconductor substrate 1 and the epitaxial layer. P-type isolation regions 25, 26, 27, 28, and 29 extend from the surface of the epitaxial layer to the surface of the semiconductor substrate 1. The isolation regions 25, 26, 27, 28, and 29 surround elements, such as transistors, Aluminum wiring layers 5 to 9 are a first level aluminum layer. A region 10 including the power transistor Q6 in the semiconductor body is surrounded by the isolation regions 25 and 26. The N-type epitaxial layer in the power transistor-forming region 10 is a collector region of the power transistor Q6. A region 11 including the power transistor Q3 is surrounded by the isolation regions 26 and 27. The N-type epitaxial layer of the power transistor-forming region 11 is a collector region of the power transistor Q3. An N-type isolation region 12 is located between the power transistors Q1 to Q6 and the small-signal circuit 40. The isolation region 12 is an N-type island of the epitaxial layer. The structure includes a glass coating 13 and an aluminum wiring layer 14 as a second level aluminum layer. An interlayer insulation layer 16 includes a through hole 15. A contact hole 17 extends through an insulation layer 18. QS is a parasitic transistor. Rcs1 to Rcs3 and Rcs are parasitic resistors. Ic1 to Ic3 and Ics are parasitic currents.
Referring to FIG. 16 and FIG. 17, the collector region of each of the power transistors Q1 to Q3 is connected to the aluminum wiring layer 8 through the through hole 15 of the insulation layer 18. The aluminum wiring layer 8 is connected to the power supply node VM. The base regions of each of the power transistors Q1 to Q6 are P-type regions on the respective collector regions. The base regions of each of the power transistors Q1 to Q6 are connected to respective aluminum wiring layers through the through hole 15 in the insulation layer 18. The aluminum wiring layer corresponding to the base regions of each of the power transistors Q1 to Q6 is connected to control signal supply circuits 45 to 50, to be described later, of the small-signal circuit. To simplify the illustration, details are omitted.
The emitter region of each of the power transistors Q1 to Q6 is an N-type region on the respective base region. The emitter regions of each of the power transistors Q4 to Q6 are connected to the aluminum wiring layer 6 through the through hole 15 of the insulation layer 18. The aluminum wiring layer 6 is connected to the ground potential node through the resistor 17. The emitter regions of each of the power transistors Q1 to Q3 and the collectors of each of the power transistors Q4 to Q6, respectively, are electrically connected to the aluminum wiring layer 14. The aluminum wiring layer 14 is connected to the corresponding terminals 21 to 23 through lead wires.
The isolation region 12 is connected to the aluminum wiring layer 9 through the through hole 15 of the insulation layer 18. The aluminum wiring layer 9 is connected to the power supply node Vcc.
The resistor region 30 in the small-signal circuit 40 is located in the epitaxial layer surrounding the isolation regions 28 and 29. A resistor is a P-type region in the resistor region 30. The P-type region for the resistor is connected to the aluminum wiring layer through the through hole 15 in the insulation layer 18. The transistor region 31 in the small-signal circuit 40 is located in the epitaxial layer surrounding the isolation region 29. The collector region of a transistor is an N-type epitaxial layer of the transistor region 31. The base region of a transistor is the P-type region on the collector region of the transistor. The emitter region of the transistor is the N-type region on the base region of the transistor. The collector, base, and emitter regions are connected to the respective aluminum wiring layers through the through hole 15 of the insulation layer 18. To simplify the illustration, a detailed description of the devices is omitted here.
Referring to FIGS. 13 to 17, the operation of the parasitic transistor QS will now be described. An assumption is made that the potential of the terminal 21 is voltage V when the power transistors Q3 and Q5 of the motor drive circuit 100 have been turned on and a current is flowing from the coil LU to the coil LV of the motor 200. If the current is switched to the direction from the coil LW to the coil LV as a result of control by the motor drive circuit 100, the flow of current in the coil LU is abruptly interrupted. Therefore, inductive energy stored in the coil LU is discharged through a parasitic diode formed between the epitaxial layer of the transistor Q6, which is the collector region, and the semiconductor substrate 1. When the state of activation is shifted from the transistor Q3 to the transistor Q1 and the direction of the current that flows in the coil is shifted as described above, the potential of the collector electrode of the transistor Q6 is transitionally changed to a negative voltage from a positive voltage, as shown in FIG. 15.
Therefore, the potential of the emitter region of the NPN parasitic transistor QS is lower than the potential of the base region of the NPN parasitic transistor QS. The NPN parasitic transistor QS is formed by the collector region of the power transistor Q6, the isolation regions 25 and 26 surrounding the transistor-forming region 10 for the power transistor Q6, and the adjacent epitaxial layer surrounded by the isolation region, such as the collector region of the transistor Q3, and the isolation region 12. The epitaxial layer is the resistor region 30 in the small-signal circuit 40, and the collector region of the transistor in the small-signal circuit 40, etc., as shown in FIG. 17. The isolation region 26 is electrically connected to the ground potential node at its surface.
Thus, the NPN parasitic transistor QS is turned on. The parasitic NPN transistor QS introduces collector current Ic from the adjacent epitaxial layer surrounded by the isolation region. The level of the collector current Ic is raised in the epitaxial layers adjacent to the collector region of the power transistor Q6 in inverse proportion to the distance to the collector region of the power transistor Q6.
In FIG. 17, the collector current Ic1 is introduced from the collector region of the power transistor Q3, the collector current Ic2 is introduced from the isolation region 12, the collector current Ic3 is introduced from the epitaxial layer of the resistor region 30 in the small-signal circuit 40, and the collector current Ics is introduced from the epitaxial layer of the transistor region 31 in the small-signal circuit 40. The total of these collector currents is Ic; that is, the collector currents satisfy the relationship Ic=Ic1+Ic2+Ic3+. . . +Ics. Note that the resistors Rcs1 to Rcs3 and Rcs, as shown in FIG. 17, are series-connected resistor components of the parasitic NPN transistor QS formed by the epitaxial layer, including the collector of the parasitic NPN transistor QS. The series resistor component Rc of the collector (the total of the series resistor components of the parasitic NPN transistor) increases in proportion to the distance from the transistor-forming region 10 for the power transistor Q6. The epitaxial layer of the transistor region 31 in the small-signal circuit 40, which is affected most considerably when the parasitic NPN transistor QS has introduced the collector current, is distant from the power transistor. Therefore, Rc is enlarged, reducing Ics.
FIG. 18 is a diagram showing a pattern of the small-signal circuit 40 on a semiconductor body including a 120.degree. -matrix circuit 41, a control amplifier circuit (CTL AMP) 42, a triple differential amplifier circuit 43, a sub-circuit TSD (terminal shut down) 44, and control signal generating circuits 45 to 48. The type and configuration of the devices may, of course, be varied arbitrarily to adapt a motor that must be controlled. The small-signal circuit 40 receives a signal Hu.sup.+, Hu.sup.-, Hv.sup.+, Hv.sup.-, Hw.sup.+, Hw.sup.-, generated by a Hall device located in the motor 200 and indicating the position of the rotor of the motor 200, to control the period during which the power transistors Q1 to Q6 in the motor drive circuit 100 are supplied with power corresponding to the detected position of the rotor.
The structure will now be described somewhat further in detail. The positional relationship among the phases as the time elapses is calculated in response to position signals Hu.sup.+, Hu.sup.-, Hv.sup.+, Hv.sup.-, Hw.sup.+, and Hw.sup.- generated by the Hall devices for the phases U, V, and W. The base electrodes of the power transistors Q1 to Q6 in the motor drive circuit 100 are controlled through the triple differential amplifier circuit 43 and the control signal generating circuits 45 to 50. The control amplifier circuit 42 is a section for controlling the triple differential amplifier circuit 43 in response to a control signal generated by a control unit, such as a computer. A portion 44 includes a variety of sub-units, for example, a TSD circuit, a constant voltage source, a power supply circuit, and the like.
As described above, the parasitic transistor QS may be turned on and affect the other circuits if the potential of the emitter region of the NPN transistor becomes lower than the ground potential. For example, the epitaxial layer of the transistor region 31 in the small-signal circuit 40 having a multiplicity of high-impedance devices raises a critical problem, contributing to malfunctioning in the control of the motor drive circuit 100. The circuit malfunctions if a current is extracted.
Accordingly, the conventional semiconductor device has an NPN transistor having a collector region connected to the power supply node and the N-type isolation region 12 is disposed between the small-signal circuit 40 and the motor drive circuit 100, so the potential of region 12 can be made lower than the ground potential.
Moreover, the inside portion of the small-signal circuit 40 has a device (such as a resistor, refer to the epitaxial layer of the resistor region 30 shown in FIG. 17) so that the N-type isolation region 12 is connected to the power supply node Vcc and disposed between the small-signal circuit 40 and the motor drive circuit 100. As described above, in this structure, the collector current Ic, required by the parasitic transistor QS, flows to the emitter region of the power transistors Q4 to Q6 from the N-type isolation region 12 connected to the power supply node Vcc to minimize the collector current Ics flowing from the collector region of the transistor in the small-signal circuit 40.
However, there arise problems. (1) The conventional semiconductor device cannot easily eliminate the influence of the collector current Ic of the parasitic transistor QS due to parasitic circuit elements. To reduce the influence, the area of, for example, the N-type isolation region 12 connected to the power supply node Vcc must be enlarged so the cost of the chip cannot be reduced. (2) A large amount of electrical power is consumed because the collector current Ic of the parasitic transistor QS flows from the power supply node Vcc to relieve the current attributable to the parasitic circuit elements.